Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials. In the layer sequence, a memory layer is arranged between confinement layers that have a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region that is located within a semiconductor body and a gate electrode that is arranged above the channel region and is provided to control the channel by means of an applied electric voltage. Charge carriers moving from source to a drain through the channel region are accelerated and gain enough energy to be able to pass the lower confinement layer and to be trapped in the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), which is incorporated herein by reference, describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide, which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm. Two bits of information can be stored in every memory cell.
Typical applications of memory products require a steady miniaturization of the memory cells. A reduction of the area that is required by an individual memory cell can be obtained by shrinking the cell structure or by an increase of the number of bits that can be stored within one memory cell transistor structure. The area of memory cell arrays can be reduced if the memory cell transistors are arranged in trenches that are formed at the surface of the semiconductor substrate. Such an arrangement renders U-shaped transistor channels, which comprise a much larger channel length than planar transistors. This is especially favorable in the case of charge-trapping memory cells described above.
The programming of charge-trapping memory cells is effected with relatively high drain-gate voltages. A punch-through between source and drain is avoided by the sufficiently large channel length. On the other hand, a punch-through can also occur between neighboring cell transistors. This limits the possible minimum pitch of the memory cell arrangement. A further problem is the injection of avalanche hot electrons into the memory layer of the adjacent cell transistor. This is due to the fact that the programming takes place while a high voltage is applied also to the wordlines of both neighboring transistors.